
Si5040
Rev. 1.3 87
Reset settings = 0000 0010
Register 156. TxdPathConfig
Bit D7 D6 D5 D4 D3 D2 D1 D0
Name dinvert clkOnLOS SquelchOnTxLOL SquelchOnTxLOS Squelch FIFOAutoReset FIFOReset
Type R R/W R/W R/W R/W R/W R/W R/W
Bit Name Function
7 Reserved Read returns zero.
6dinvertData Invert.
0 = Normal operation.
1 = TXDOUT+ and TXDOUT– outputs (pins 30, 29) are inverted.
5clkOnLOSClock Output on Transmitter Loss of Signal.
0 = Normal operation.
1 = 622 MHz clock output on TXDOUT+ and TXDOUT– on transmitter LOS condition.
4 SquelchOnTxLOL Data Squelch on Transmit Loss of Lock.
0 = Normal operation.
1 = squelch TXDOUT output (pins 30, 29) on transmitter Loss of Lock condition.
3 SquelchOnTxLOS Data Squelch on Transmit Loss of Signal.
0 = Normal operation.
1 = squelch TXDOUT output (pins 30, 29) on transmitter Loss of Signal condition.
2 Squelch Data Squelch.
0 = Normal operation.
1 = squelch TXDOUT output (pins 30, 29).
1 FIFOAutoReset FIFO Auto Reset.
0 = No reset of transmit FIFO on FIFO error.
1 = automatically reset transmit FIFO on FIFO underflow or overflow. FIFO pointer is
reset to center value and FIFO is cleared.
0 FIFOReset FIFO Reset.
0 = Normal operation.
1 = reset transmit FIFO. FIFO pointer is reset to center value and FIFO is cleared.
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