
Si5040
58 Rev. 1.3
Reset settings = 0000 0000
Reset settings = 0000 0000
Register 21. sliceLvl
BitD7D6D5D4D3D2D1D0
Name sliceLvl[7:0]
Type R/W
Bit Name Function
7:0 sliceLvl[7:0] Slice Level.
Least significant byte of slice level setting. 2's compliment signed value.
Absolute mode: 7FFFH = maximum slice offset = +240 mV
8000H = minimum slice offset = –240 mV
Proportional Mode: Threshold = 50% + sliceLvl/65536 x 100
Constant Duty Cycle Mode: 7A7AH = maximum duty cycle = ~74%
8586H = minimum duty cycle = ~26%
Register 22. sliceLvl
Bit D15 D14 D13 D12 D11 D10 D9 D8
Name sliceLvl[15:8]
Type R/W
Bit Name Function
15:8 sliceLvl[15:8] Slice Level.
Most significant byte of slice level setting. 2s compliment signed value.
Absolute mode: 7FFFH = maximum slice offset = +240 mV
8000H = minimum slice offset = –240 mV
Proportional Mode: Threshold = 50% + sliceLvl/65536 x 100
Constant Duty Cycle Mode: 7A7AH = maximum duty cycle = ~74%
8586H = minimum duty cycle = ~26%
Note: The slice level defined by Register 22 and 21 gets updated together after Register 21, the
least significant byte of the 16-bit field, has been written. Prior to writing Register 21, the
value written to Register 22 is stored into a mirroring register first. Any read to Register 22
prior to writing Register 21 will not return the intended value.
Duty Cycle 50%
sliceLvl 15:0
1310
---------------------------------------
%+=
Duty Cycle 50%
sliceLvl 15:0
1310
---------------------------------------
%+=
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