Datacom Systems D56 Spezifikationen PDF herunterladen (Seite 28)

Si5040

28 Rev. 1.3

5.9. Receiver Phase Adjust

The Si5040 receiver supports programmable sample phase adjust. The sampling point may be advanced or

delayed in time by adjusting the value loaded into the RxPhaseAdjust register (Register 24). The range of

adjustment is ±12 ps.

5.10. Receive Clock Multiplier Unit

The Si5040 receiver incorporates a DSPLL

-based clock multiplier unit (CMU) that attenuates the jitter on data

recovered from the line interface. This makes it much easier to significantly exceed the jitter requirements for

10 Gbit SONET, Ethernet, and Fibre Channel applications. The CMU is rate-adaptable across the entire range of

device operation. Note that when the ltr bit or ltrOnLOS bit in Register 7 is set to 1, the receive CMU is locked to the

reference clock.

The receiver CMU supports 380 kHz bandwidth (cmuBandwidth[3:0] at Register 6 = 0100).

5.11. Recommended Pre-Emphasis on the RD Signal

Even though the RD signal rise/fall time is very fast, some users may wish to add high-frequency boost to the RD

signal. This is done with an external RC network to reduce low-frequency energy, effectively boosting the high

frequencies. To compensate for loss in the circuit and maintain proper signal size and eye opening at the XFI

connector, the RD amplitude will have to increase to 700 or 800 mV. Register 56 controls the RD signal amplitude.

The resistors and capacitors can be generic low-cost components, and the circuit should be located very close to

the Si5040 RD± pins. This circuit is recommended for all XFP applications.

Figure 17. RD Pre-Emphasis Circuit

20.5

3.0 pf

5040 RD+

XFI RD+

20.5

3.0 pf

5040 RD-

274 

XFI RD-

.01 µF

274 

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Datacom Systems D56 Spezifikationen Seite 28