
Si5040
32 Rev. 1.3
Figure 18. Referenceless Mode (Mode 0)
Figure 19. Synchronous Reference Clock (Mode 1)
Figure 20. Mode 2
CDR
Equalizer
DSPLL
®
Jitter Attenuator
CMU
TD
TXDOUT
CML
XFI Recovered Data
XFI Recovered Clock
FIFO
CDR
Equalizer
DSPLL
®
Jitter Attenuator
CMU
TD
TXDOUT
CML
XFI Recovered Data
XFI Recovered Clock
FIFO
Synchronous
Reference Clock
CDR Equalizer
DSPLL
®
Jitter Attenuator
CMU
TD
TXDOUT
CML
XFI Recovered
Data
XFI Recovered
Clock
FIFO
Asynch Ref Clock (Mode 2)
Cleaned Up
Clock
Phase
out
Phase
in
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