Datacom Systems D56 Spezifikationen PDF herunterladen (Seite 61)

Si5040

Rev. 1.3 61

Reset settings = 0000 0010

BitD7D6D5D4D3D2 D1 D0

Name dinvert clkOnLOS SquelchO-

nRxLOL

SquelchO-

nRxLOS

Squelch FIFOAuto

Reset

FIFOReset

Type RR/WR/WR/WR/WR/W R/W R/W

Bit Name Function

7 Reserved Read returns zero.

6dinvertData Invert.

0 = Normal operation.

1 = RD+ and RD– outputs (pins 19, 18) inverted.

5clkOnLOSClock Output on Receive Loss of Signal.

0 = Normal operation.

1 = 622 MHz clock output on RD+ and RD– on receiver LOS condition.

4 SquelchOnRxLOL Data Squelch on Receive Loss of Lock.

0 = Normal operation.

1 = Squelch RD+ and RD– outputs (pins 19, 18) on receiver Loss of Lock condition.

3 SquelchOnRxLOS Data Squelch on Receive Loss of Signal.

0 = Normal operation.

1 = Squelch RD+ and RD– outputs (pins 19, 18) on receiver Loss of Signal condition.

2 Squelch Data Squelch.

0 = Normal operation.

1 = Squelch RD+ and RD– outputs (pins 19, 18).

1 FIFOAutoReset FIFO Auto Reset.

0 = No reset of receive FIFO on FIFO error.

1 = Automatically reset receive FIFO on FIFO underflow or overflow and clear fifoerr

bit in RXintMask register (Reg4[1]). FIFO pointer is reset to center value and FIFO is

cleared.

0 FIFOReset FIFO Reset.

0 = Normal operation.

1 = Reset receive FIFO. FIFO pointer is reset to center value and FIFO is cleared.

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Datacom Systems D56 Spezifikationen Seite 61