Datacom Systems D56 Spezifikationen Seite 35
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Si5040
Rev. 1.3 35
10. Serial Microcontroller Interface
Device control and status monitoring is supported with a selectable I
2
C or SPI-like interface. SPSEL (Pin 9)
controls which of the two serial formats is selected.
10.1. I
2
C Interface
When configured in I
2
C control mode (pin SPSEL tied low), the control interface to the Si5040 is a 2-wire bus for
bidirectional communication. The bus consists of a bidirectional serial data line (SD) and a serial clock input (SCK).
The SD pin may be configured as a CMOS output or as an open drain output using Register 2, bit 4. Fast mode
operation is supported for transfer rates up to 400 kbps as specified in the I
2
C-Bus Specification standard. A chip
select pin is provided (SS) to address the Si5040.
Figure 21 shows the command format for both read and write access. Data is always sent MSB first. Table 2 on
page 6 and Table 3 on page 8 give the dc and ac electrical parameters for the SCK and SD I/Os, respectively. The
timing specifications and timing diagram for the I
2
C bus can be found in the I
2
C-Bus Specification standard (fast
mode operation).
Figure 21. I
2
C Command Format
The device has two possible I
2
C addresses depending on the SSb pin setting. If the SSb pin is floating or externally
tied high, the device has an I
2
C address of 7d' 1000001. If the SSb pin is externally tied low, the device has an I
2
C
address of 7d' 1000000. For applications that require two Si5040 devices connected on the same I
2
C bus, each
individual device can be accessed with a unique I
2
C address depending on the SSb pin setting.
Figure 22 illustrates how the I
2
C address can be configured and what the expected value is for the first byte after
the START condition. Note that the first byte after the START condition could be either 82h or 83h depending on
whether it's a read or write. The first byte after the START condition could be either 80h or 81h depending on
whether it is a read or write.
Figure 22. Device I
2
C Address
AData AData PA1Slave AddressSAByte AddressA0Slave AddressS 1
From master to slave
From slave to master
A – Acknowledge (SD LOW)
S – START condition
P – STOP condition
Write Command
Read Command
Address auto incremented after each data read or write
PA
Data
A
Data
AByte AddressA0Slave AddressS
1 Read
0 Write
1 0 0 0 0 0
X
Per I
2
C specification, this bit is
either 1 for read or 0 for write.
Source: Fig 14 of I
2
C – Bus Specification Version 2.1
By design, this bit in the I
2
C address
is determined by the SSb pin.
- Features 1
- Applications 1
- Description 1
- Functional Block Diagram 1
- 2 Rev. 1.3 2
- TABLE OF CONTENTS 3
- Measurement 4
- 2. Electrical Specifications 5
- Table 2. DC Characteristics 6
- 8 Rev. 1.3 8
- = 1.8 V +5/–10%, T 8
- = –40 to 95 C) 8
- 10 Rev. 1.3 10
- Table 7. CMU Timing Modes 12
- Rev. 1.3 13 13
- Table 8. AC Characteristics—I 14
- C Bus Lines (SD, SCK) 14
- 765432 76543210 15
- Read Command Read Data 15
- 16 Rev. 1.3 16
- Rev. 1.3 17 17
- 4. Functional Description 18
- Normalized Output Amplitude 19
- 5.2. Limiting Amplifier 20
- Rev. 1.3 21 21
- 22 Rev. 1.3 22
- 5.5. Receiver Slice Control 23
- 5.7. Reference Clock 24
- Rev. 1.3 25 25
- 26 Rev. 1.3 26
- Rev. 1.3 27 27
- 5.9. Receiver Phase Adjust 28
- 6. Transmitter 29
- 30 Rev. 1.3 30
- Rev. 1.3 31 31
- 32 Rev. 1.3 32
- 7. Loopback Modes 33
- 8. Looptime Mode 33
- 10.1. I 35
- C Interface 35
- 10.2. SPI-Like Interface 36
- 11. Interrupt Functionality 37
- 38 Rev. 1.3 38
- Rev. 1.3 39 39
- 13. Si5040 Register Summary 40
- 44 Rev. 1.3 44
- 46 Rev. 1.3 46
- Rev. 1.3 47 47
- 48 Rev. 1.3 48
- Rev. 1.3 49 49
- 50 Rev. 1.3 50
- 52 Rev. 1.3 52
- Register 10 52
- Rev. 1.3 53 53
- 54 Rev. 1.3 54
- 56 Rev. 1.3 56
- 00 0000 0000 = 0 mV 56
- 11 1111 1111 = 1022 mV 56
- Rev. 1.3 57 57
- Rev. 1.3 59 59
- 60 Rev. 1.3 60
- Note: Default = 10 (decimal) 60
- Note: Default = 15 (decimal) 60
- Rev. 1.3 61 61
- Rev. 1.3 63 63
- Exponent 69
- 70 Rev. 1.3 70
- 72 Rev. 1.3 72
- Rev. 1.3 73 73
- 74 Rev. 1.3 74
- Rev. 1.3 75 75
- 76 Rev. 1.3 76
- Rev. 1.3 77 77
- 78 Rev. 1.3 78
- Rev. 1.3 79 79
- 80 Rev. 1.3 80
- Rev. 1.3 81 81
- 82 Rev. 1.3 82
- Rev. 1.3 83 83
- 84 Rev. 1.3 84
- Rev. 1.3 85 85
- 86 Rev. 1.3 86
- Note: Default = 1 (decimal) 86
- Note: Default = 8 (decimal) 86
- Rev. 1.3 87 87
- Bit D7 D6 D5 D4 D3 D2 D1 D0 87
- Rev. 1.3 89 89
- Rev. 1.3 95 95
- 96 Rev. 1.3 96
- 98 Rev. 1.3 98
- Rev. 1.3 99 99
- 14. Pin Descriptions: Si5040 100
- Rev. 1.3 101 101
- Input/Output 101
- 102 Rev. 1.3 102
- 15. Ordering Guide 103
- 16. Package Outline: Si5040 104
- Rev. 1.3 105 105
- DOCUMENT CHANGE LIST 106
- Revision 0.86 to Revision 1.2 107
- Revision 1.2 to Revision 1.3 107
- CONTACT INFORMATION 108
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