
Si5040
14 Rev. 1.3
Table 8. AC Characteristics—I
2
C Bus Lines (SD, SCK)
(V
DD
= 1.8 V +5/–10%, T
A
= –40 to 95 C)
Parameter Symbol Test Condition Min Typ Max Unit
Pin Capacitance C
II2C
— — 10 pF
Table 9. Switching Characteristics—Serial Microcontroller Interface
2
V
DD
= 1.8 V +5/–10%, V
DDIO
= 3.3 V ±10%, T
A
= –40 to 95 °C, C
L
=20pF
Parameter Symbol Test
Conditions
Min Typ Max Unit
Cycle Time SCK t
c
100 — — ns
Rise Time, SCK t
r
20–80% — — 25 ns
Fall Time, SCK t
f
20–80% — — 25 ns
Low Time, SCK t
lsc
20–20% 30 — — ns
High Time, SCK t
hsc
80–80% 30 — — ns
Delay Time, SCK Fall to SD Active t
d1
——25ns
Delay Time, SCK Fall to SD Transition t
d2
——25ns
Delay Time, SS
Rise to SD Tri-state
1
t
d3
——25ns
Setup Time, SS
to SCK Fall t
su1
25 — — ns
Hold Time, SS
to SCK Rise t
h1
20 — — ns
Setup Time, SD to SCK Rise t
su2
25 — — ns
Hold Time, SD to SCK Rise t
h2
20 — — ns
Delay Time between Slave Selects t
cs
25 — — ns
Notes:
1. SD is designed to be tristated by the release of the chip select signal (the rising edge of the SS
).
2. All timing is referenced to the 50% level of the waveform unless otherwise noted. Input test levels are V
IH
=V
DD
–0.4 V,
V
IL
=0.4V
Kommentare zu diesen Handbüchern