Datacom Systems D56 Spezifikationen Seite 40
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Si5040
40 Rev. 1.3
13. Si5040 Register Summary
Any reserved bits listed in the table below or reserved registers (23, 54–55, 58–76, 78–83, 86–97, 99–105, 110–
130, 140–144, 148–151, 182–183, 185–204, 206–225, and 227–255) must not be written to a non-default value.
All reserved bits have the default values shown below.
Reg Name Default Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Receiver
0 Part Identifier 40h Identifier[7:0]
1 Part Identifier 30h Revision[3:0] Identifier[3:0]
2 ChipConfig1 58h losOpen
Drain
intOpen
Drain
intEnable spiOpen
Drain
Reserved lineside-
Loopback
XFILoop-
back
refClkFreq
3 RxChipConfig2 0h Reserved Reserved Reserved Reserved Reserved Reserved Reserved RxPdn
4 RxintMask 0h Reserved refLOS LOS LOL fifoErr tpErrAlarm tpSyncLos sqmAlarm
5 RxintStatus
(Sticky Bits)
0h Reserved refLOS LOS LOL fifoErr tpErrAlarm tpSyncLos sqmAlarm
6 RxCmuConfig 40h cmuBandwidth[3:0] Reserved Reserved
7 RxConfig 15h Reserved lolOnLOS ltrOnLOS CDRLT-
DATA
uselolMode lolMode ltr rxRefclkEn
8 RxCalConfig 0h Reserved Reserved Reserved Reserved hardRecal VCOCAL[1:0] swReset
9 RxAlarmStatus 0h Reserved refLOS LOS LOL fifoErr tpErrAlarm tpSyncLos sqmAlarm
10 RxLosCtrl 1h Reserved Reserved Reserved Reserved sqmLosEn dLosEn[1:0] aLosEn
11 RxLosStatus 0h Reserved Reserved Reserved sqmLos dLOSlast-
Trigger
dLOS aLOS LOS
12 aLosThresh Fh aLOSThresh[7:0]
13 aLosThresh2 70h aLosHyst[3:0] Reserved aLosThresh[1:0]
15 peakDet 0h peakDet[7:0]
16 peakDet 0h Reserved Reserved Reserved Reserved Reserved Reserved peakDet[1:0]
17 RxdLosAssert-
Thresh
5h RxdLosAssertThresh[7:0]
18 RxdLos
ClearThresh
60h RxdLosClearThresh[7:0]
20 sliceConfig 11h Reserved Reserved Reserved Reserved Reserved sliceEn[2:0]
21 sliceLvl 0h sliceLvl[7:0]
22 sliceLvl 0h sliceLvl[15:8]
24 RxphaseAdjust 0h Reserved RxphaseAdjust[6:0]
25 RxSqmValue N/A Reserved Reserved RxSqmValue[5:0]
26 RxSqmConfig 29h RxSqmThresh[5:0] Reserved Reserved
27 RxSqmDeassert-
Thresh
Fh Reserved Reserved RxSqmDeassertThresh[5:0]
28 RxdPathConfig 2h Reserved dinvert clkOnLOS SquelchOn-
RxLOL
SquelchOn-
RxLOS
Squelch FIFOAu-
toReset
FIFOReset
29 RxtpSel 0h tpChkInvert tpChkSel[2:0] tpGenInvert tpGenSel[2:0]
- Features 1
- Applications 1
- Description 1
- Functional Block Diagram 1
- 2 Rev. 1.3 2
- TABLE OF CONTENTS 3
- Measurement 4
- 2. Electrical Specifications 5
- Table 2. DC Characteristics 6
- 8 Rev. 1.3 8
- = 1.8 V +5/–10%, T 8
- = –40 to 95 C) 8
- 10 Rev. 1.3 10
- Table 7. CMU Timing Modes 12
- Rev. 1.3 13 13
- Table 8. AC Characteristics—I 14
- C Bus Lines (SD, SCK) 14
- 765432 76543210 15
- Read Command Read Data 15
- 16 Rev. 1.3 16
- Rev. 1.3 17 17
- 4. Functional Description 18
- Normalized Output Amplitude 19
- 5.2. Limiting Amplifier 20
- Rev. 1.3 21 21
- 22 Rev. 1.3 22
- 5.5. Receiver Slice Control 23
- 5.7. Reference Clock 24
- Rev. 1.3 25 25
- 26 Rev. 1.3 26
- Rev. 1.3 27 27
- 5.9. Receiver Phase Adjust 28
- 6. Transmitter 29
- 30 Rev. 1.3 30
- Rev. 1.3 31 31
- 32 Rev. 1.3 32
- 7. Loopback Modes 33
- 8. Looptime Mode 33
- 10.1. I 35
- C Interface 35
- 10.2. SPI-Like Interface 36
- 11. Interrupt Functionality 37
- 38 Rev. 1.3 38
- Rev. 1.3 39 39
- 13. Si5040 Register Summary 40
- 44 Rev. 1.3 44
- 46 Rev. 1.3 46
- Rev. 1.3 47 47
- 48 Rev. 1.3 48
- Rev. 1.3 49 49
- 50 Rev. 1.3 50
- 52 Rev. 1.3 52
- Register 10 52
- Rev. 1.3 53 53
- 54 Rev. 1.3 54
- 56 Rev. 1.3 56
- 00 0000 0000 = 0 mV 56
- 11 1111 1111 = 1022 mV 56
- Rev. 1.3 57 57
- Rev. 1.3 59 59
- 60 Rev. 1.3 60
- Note: Default = 10 (decimal) 60
- Note: Default = 15 (decimal) 60
- Rev. 1.3 61 61
- Rev. 1.3 63 63
- Exponent 69
- 70 Rev. 1.3 70
- 72 Rev. 1.3 72
- Rev. 1.3 73 73
- 74 Rev. 1.3 74
- Rev. 1.3 75 75
- 76 Rev. 1.3 76
- Rev. 1.3 77 77
- 78 Rev. 1.3 78
- Rev. 1.3 79 79
- 80 Rev. 1.3 80
- Rev. 1.3 81 81
- 82 Rev. 1.3 82
- Rev. 1.3 83 83
- 84 Rev. 1.3 84
- Rev. 1.3 85 85
- 86 Rev. 1.3 86
- Note: Default = 1 (decimal) 86
- Note: Default = 8 (decimal) 86
- Rev. 1.3 87 87
- Bit D7 D6 D5 D4 D3 D2 D1 D0 87
- Rev. 1.3 89 89
- Rev. 1.3 95 95
- 96 Rev. 1.3 96
- 98 Rev. 1.3 98
- Rev. 1.3 99 99
- 14. Pin Descriptions: Si5040 100
- Rev. 1.3 101 101
- Input/Output 101
- 102 Rev. 1.3 102
- 15. Ordering Guide 103
- 16. Package Outline: Si5040 104
- Rev. 1.3 105 105
- DOCUMENT CHANGE LIST 106
- Revision 0.86 to Revision 1.2 107
- Revision 1.2 to Revision 1.3 107
- CONTACT INFORMATION 108
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