Datacom Systems D56 Spezifikationen Seite 33
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Si5040
Rev. 1.3 33
7. Loopback Modes
The Si5040 supports XFI Loopback, Lineside Loopback, and Looptime modes.
7.1. XFI Loopback
The Si5040 is configured in the XFI Loopback mode by writing to the ChipConfig1 register (Register 2). The Si5040
is configured in the XFI Loopback mode by writing to the ChipConfig1 register (Register 2). Data on the TD input is
retimed and output on the RD output. The clock recovered from the XFI data (TD) is used as the timing source for
the RD output. For this reason, RX VCOCAL (Register 8, Bit [2:1]) must be set to reference or auto mode. If the
data from the transmitter is not required at the TXDOUT output pins, it may be disabled by writing to the transmitter
Squelch bit in the dPath register (Register 156, bit 2). Data on the TD input is retimed and output on the RD output.
The clock recovered from the XFI data (TD) is used as the timing source for the RD output.
7.2. Lineside Loopback
The Si5040 is configured in the Lineside Loopback mode by writing to the ChipConfig1 register (Register 2). Data
received on the receiver input (RXDIN) is output on the transmitter (TXDOUT) output. Since in this mode the clock
recovered from the receiver input is used as the timing source for the transmit CMU, TX VCOCAL (Register 136,
Bit [2:1]) must be in reference or auto mode. If the data from the receiver is not required at the XFI interface, it may
be disabled by writing to the receiver Squelch bit in the dPath register (Register 28, bit 2).
8. Looptime Mode
The Si5040 supports looptime mode for applications in which it is desirable to time the transmitter off the receiver
clock. Data received at the XFI interface (TD) is retimed using the clock recovered from the receiver (RXDIN). As a
result of the transmit CMU jitter attenuation feature in the Si5040, with the appropriate setting of the CMU
bandwidth (set in Register 134), the jitter on the recovered clock is significantly attenuated so that the data on the
transmit output will be compliant with the datacom and telecom standards supported by the Si5040. A FIFO within
the data path accommodates any jitter differences between the serial data and the CMU line-rate clock. Looptime
mode is enabled by writing to the TxCmuConfig register (Register 134).
- Features 1
- Applications 1
- Description 1
- Functional Block Diagram 1
- 2 Rev. 1.3 2
- TABLE OF CONTENTS 3
- Measurement 4
- 2. Electrical Specifications 5
- Table 2. DC Characteristics 6
- 8 Rev. 1.3 8
- = 1.8 V +5/–10%, T 8
- = –40 to 95 C) 8
- 10 Rev. 1.3 10
- Table 7. CMU Timing Modes 12
- Rev. 1.3 13 13
- Table 8. AC Characteristics—I 14
- C Bus Lines (SD, SCK) 14
- 765432 76543210 15
- Read Command Read Data 15
- 16 Rev. 1.3 16
- Rev. 1.3 17 17
- 4. Functional Description 18
- Normalized Output Amplitude 19
- 5.2. Limiting Amplifier 20
- Rev. 1.3 21 21
- 22 Rev. 1.3 22
- 5.5. Receiver Slice Control 23
- 5.7. Reference Clock 24
- Rev. 1.3 25 25
- 26 Rev. 1.3 26
- Rev. 1.3 27 27
- 5.9. Receiver Phase Adjust 28
- 6. Transmitter 29
- 30 Rev. 1.3 30
- Rev. 1.3 31 31
- 32 Rev. 1.3 32
- 7. Loopback Modes 33
- 8. Looptime Mode 33
- 10.1. I 35
- C Interface 35
- 10.2. SPI-Like Interface 36
- 11. Interrupt Functionality 37
- 38 Rev. 1.3 38
- Rev. 1.3 39 39
- 13. Si5040 Register Summary 40
- 44 Rev. 1.3 44
- 46 Rev. 1.3 46
- Rev. 1.3 47 47
- 48 Rev. 1.3 48
- Rev. 1.3 49 49
- 50 Rev. 1.3 50
- 52 Rev. 1.3 52
- Register 10 52
- Rev. 1.3 53 53
- 54 Rev. 1.3 54
- 56 Rev. 1.3 56
- 00 0000 0000 = 0 mV 56
- 11 1111 1111 = 1022 mV 56
- Rev. 1.3 57 57
- Rev. 1.3 59 59
- 60 Rev. 1.3 60
- Note: Default = 10 (decimal) 60
- Note: Default = 15 (decimal) 60
- Rev. 1.3 61 61
- Rev. 1.3 63 63
- Exponent 69
- 70 Rev. 1.3 70
- 72 Rev. 1.3 72
- Rev. 1.3 73 73
- 74 Rev. 1.3 74
- Rev. 1.3 75 75
- 76 Rev. 1.3 76
- Rev. 1.3 77 77
- 78 Rev. 1.3 78
- Rev. 1.3 79 79
- 80 Rev. 1.3 80
- Rev. 1.3 81 81
- 82 Rev. 1.3 82
- Rev. 1.3 83 83
- 84 Rev. 1.3 84
- Rev. 1.3 85 85
- 86 Rev. 1.3 86
- Note: Default = 1 (decimal) 86
- Note: Default = 8 (decimal) 86
- Rev. 1.3 87 87
- Bit D7 D6 D5 D4 D3 D2 D1 D0 87
- Rev. 1.3 89 89
- Rev. 1.3 95 95
- 96 Rev. 1.3 96
- 98 Rev. 1.3 98
- Rev. 1.3 99 99
- 14. Pin Descriptions: Si5040 100
- Rev. 1.3 101 101
- Input/Output 101
- 102 Rev. 1.3 102
- 15. Ordering Guide 103
- 16. Package Outline: Si5040 104
- Rev. 1.3 105 105
- DOCUMENT CHANGE LIST 106
- Revision 0.86 to Revision 1.2 107
- Revision 1.2 to Revision 1.3 107
- CONTACT INFORMATION 108
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